Peripheral Component Interface (PCI) express (PCIe) devices promise to provide more data throughput when compared with previously available PCI or PCI extended (PCI-X) devices. Some PCIe implementations may utilize credits to balance the sharing of available bandwidth on a PCIe bus amongst various devices.
However, when implementing PCIe with infinite completion credits, transactions may have to be processed at the same rate as they are received. More specifically, transactions containing the largest possible payload may require 1025 clock cycles, whereas the smallest transactions may be received in a single clock cycle. The two differing types of transactions may arrive back to back. To make matters more complicated, the link may flag a transaction as bad at the end, e.g., after having written all the data to the backend of a PCIe device and the logic would have to rewind the address and wait for a replay of the transaction. Accordingly, such implementations may be inefficient and suffer from latency.